COMPRO X800 - START UP GUIDE Especificaciones descargar pdf (Pagina 18)

18 _____________________________________________________________________________________

MAX9249

Gigabit Multimedia Serial Link

Serializer with LVDS System Interface

the embedded serial clock and then samples, decodes,

and descrambles before outputting the data. Figures

15 and 16 show the serial-data packet format before

scrambling and 8B/10B coding. In 3-channel or 4-chan-

nel mode, 21 or 28 bits come from the RXIN_ _ LVDS

inputs. Control bits can be mapped to DIN27 and DIN28

in 4-channel mode. The audio channel bit (ACB) con-

tains an encoded audio signal derived from the three I

inputs (SD/CNTL0, SCK, and WS). The forward control-

channel (FCC) bit carries the forward control data. The

last bit (PCB) is the parity bit of the previous 23 or 31 bits.

Reserved Bit (RES)

In 4-channel mode, the MAX9249 serializes all bits of all

four lanes including RES by default. Set DISRES (D4 of

RES.

Reverse Control Channel

The MAX9249 uses the reverse control channel to

receive I

C/UART and interrupt signals from the GMSL

deserializer in the opposite direction of the video stream.

The reverse control channel and forward video data

coexist on the same twisted pair forming a bidirectional

link. The reverse control channel operates independently

from the forward control channel. The reverse control

channel is available 500Fs after power-up. The MAX9249

temporarily disables the reverse control channel for

350Fs after starting/stopping the forward serial link.

Data-Rate Selection

The MAX9249 uses the DRS input to set the RXCLKIN_

frequency. Set DRS high for an RXCLKIN_ frequency of

6.25MHz to 12.5MHz (4-channel mode) or 8.33MHz to

16.66MHz (3-channel mode). Set DRS low for normal

operation with an RXCLKIN_ frequency of 12.5MHz

to 78MHz (4-channel mode) or 16.66MHz to 104MHz

(3-channel mode).

Figure 14. VESA Standard Panel Clock and Bit Assignment

Figure 15. 3-Channel Mode Serial Link Data Format

CYCLE N-1 CYCLE N

RXIN0+/RXIN0-

RXCLKIN+

RXCLKIN-

RXIN1+/RXIN1-

RXIN2+/RXIN2-

R0 G0 R5 R4 R3 R2 R1 R0

G2 G1 B1 B0 G5 G4 G3 G2 G1

B3 B2 DE VS HS B5 B4 B3 B2

RXIN3+/RXIN3-

R7 R6 RES B7 B6 G7 G6 R7 R6

NOTE: LOCATIONS OF THE RGB DATA AND CONTROL SIGNALS ARE

SET ACCORDING TO VESA STANDARD PANEL BITMAP.

DIN0

LVDS

DATA

(3 CHANNELS)

DIN1 DIN17 DIN18 DIN19 DIN20 ACB FCC PCB

24 BITS

AUDIO

CHANNEL BIT

FORWARD

CONTROL-

CHANNEL BIT

PACKET

PARITY

CHECK BIT

R0 R1 B5 HS VS DE

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 35 36

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