COMPRO X800 - START UP GUIDE Especificaciones descargar pdf (Pagina 19)

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MAX9249

Gigabit Multimedia Serial Link

Serializer with LVDS System Interface

Figure 16. 4-Channel Mode Serial Link Data Format

Audio Channel

The I

S audio channel supports audio sampling rates

from 8kHz to 192kHz and audio word lengths from 4 bits

to 32 bits. The audio bit clock (SCK) does not have to

be synchronized with RXCLKIN_. The MAX9249 auto-

matically encodes audio data into a single bit stream

synchronous with RXCLKIN_. The GMSL deserializer

decodes the audio stream and stores audio words in a

FIFO. Audio rate detection uses an internal oscillator to

continuously determine the audio data rate and output

the audio in I

S format. The audio channel is enabled by

default. When the audio channel is disabled, the audio

data on the MAX9249 and GMSL deserializer is treated

as a control pin (CNTL0).

Low RXCLKIN_ frequencies limit the maximum audio

sampling rate. Table 3 lists the maximum audio sam-

pling rate for various RXCLKIN_ frequencies. Spread-

spectrum settings do not affect the I

S data rate or WS

clock frequency.

Control Channel and Register Programming

The control channel is available for the FC to send

and receive control data over the serial link simultane-

ously with the high-speed data. Configuring the CDS pin

allows the FC to control the link from either the MAX9249

or the GMSL deserializer side to support video-display or

image-sensing applications.

The control channel between the FC and MAX9249 or

GMSL deserializer runs in base mode or bypass mode

according to the mode selection (MS) input of the device

connected to the FC. Base mode is a half-duplex control

channel and the bypass mode is a full-duplex control

channel. In base mode, the FC is the host and can

access the registers of both the MAX9249 and GMSL

deserializer from either side of the link by using the GMSL

Table 3. Maximum Audio WS Frequency (kHz) for Various RXCLKIN_ Frequencies

DIN21

LVDS

DATA

(RXIN3_)

DIN22 DIN25 DIN26 DIN27 DIN28 ACB FCC PCB

32 BITS

AUDIO

CHANNEL/CNTL0

BIT

FORWARD

CONTROL-

CHANNEL BIT

PACKET

PARITY

CHECK BIT

R6 R7 B6

DIN24

DIN23

G6 B7 CNTL2

RES/CNTL1

DIN1

LVDS

DATA

(RXIN[2:0]_)

DIN18 DIN19 DIN20

DIN0

R0 HS

DIN17

B5 VS DE

*DIN27 FROM LVDS DATA (RXIN3_) OR EXTERNAL PIN (CNTL1).

NOTE: LOCATIONS OF THE LVDS RGB DATA AND CONTROL SIGNALS

ARE SET ACCORDING TO THE VESA STANDARD PANEL BITMAP.

WORD LENGTH

(BITS)

RXCLKIN_ FREQUENCY

(DRS = LOW)

(MHz)

RXCLKIN_ FREQUENCY

(DRS = HIGH)

(MHz)

12.5 15 16.6 > 20 6.25 7.5 8.33 > 10

8 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192

16 > 192 > 192 > 192 > 192 > 192 > 192 > 192 > 192

18 185.5 > 192 > 192 > 192 185.5 > 192 > 192 > 192

20 174.6 > 192 > 192 > 192 174.6 > 192 > 192 > 192

24 152.2 182.7 > 192 > 192 152.2 182.7 > 192 > 192

32 123.7 148.4 164.3 > 192 123.7 148.4 164.3 > 192

1 2 ... 14 15 16 17 18 19 20 21 22 23 24 ... 35 36

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